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features ? minimal external circuitry requirements, no rf components on the pc board except matching to the receiver antenna high sensitivity, especi ally at low data rates sso20 and so20 package fully integrated vco supply voltage 4.5v to 5.5v, operat ing temperature range ?40c to +105c single-ended rf input for easy adaptation to l/4 antenna or printed antenna on pcb low-cost solution due to high integration level various types of protocols supported (i .e., pwm, manchester and bi-phase) distinguishes the signal strength of se veral transmitters via rssi (received signal strength indicator) esd protection according to mil-std. 883 (4kv hbm) high image frequency suppressi on due to 1 mhz if in conjunction with a saw front- end filter, up to 40 db is thereby achievable with newer saws power management (polling) is possible by means of a separate pin via the microcontroller receiving bandwidth bif = 600 khz 1. description the t5744 is a pll receiver device for the receiving range of f 0 = 300 mhz to 450 mhz. it is developed for the demands of rf low-cost data communication sys- tems with low data rates and fits for most types of modulation schemes including manchester, bi-phase and most pwm protocols. its main applications are in the areas of telemetering, security technology and keyless-entry systems. figure 1-1. system block diagram demod. if amp lna vco pll xto data interface t5744 1...3 c power amp. xto vco pll u2741b antenna antenna uhf ask/fsk remote control transmitter uhf ask remote control receiver encoder atarx9x 1 li cell keys uhf ask receiver t5744 rev. 4521c?rke?05/05
2 4521c?rke?05/05 t5744 2. pin configuration figure 2-1. pinning so20 and sso20 table 2-1. pin description pin symbol function 1 br_0 baud rate select lsb 2 br_1 baud rate select msb 3 cdem lower cut-off frequency data filter 4 avcc analog power supply 5 agnd analog ground 6 dgnd digital ground 7 mixvcc power supply mixer 8 lnagnd high-frequency ground lna and mixer 9lna_inrf input 10 nc not connected 11 lfvcc power supply vco 12 lf loop filter 13 lfgnd ground vco 14 xto crystal oscillator 15 dvcc digital power supply 16 mode selecting 433.92 mhz /315 mhz low: 315 mhz (usa) high: 433.92 mhz (europe) 17 rssi output of the rssi amplifier 18 test test pin, during operation at gnd 19 enable selecting operation mode low: sleep mode high: receiving mode 20 data data output 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 avcc agnd dgnd mixvcc lnagnd lna_in br_1 cdem rssi mode xto lfgnd lf enable test nc lfvcc data dvcc br_0 t5744
3 4521c?rke?05/05 t5744 figure 2-2. block diagram 3. rf front end the rf front end of the receiver is a heterodyne co nfiguration that converts the input signal into a 1-mhz if signal. according to figure 2-2 , the front end consists of an lna (low-noise ampli- fier), lo (local oscillator) , a mixer and rf amplifier. the lo generates the carrier frequency for the mixe r via a pll synthesize r. the xto (crystal oscillator) generates th e reference frequency f xto . the vco (voltage-controlled oscillator) gen- erates the drive voltage frequency f lo for the mixer. f lo is dependent on the voltage at pin lf. f lo is divided by factor 64. the divided frequency is compared to f xto by the phase frequency detec- tor. the current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage vlf for the vc o. by means of that configuration, vlf is controlled in a way that f lo /64 is equal to f xto . if f lo is determined, f xto can be calculated using the following formula: f xto = f lo /64 ask- demodulator and data filter rssi if amp if am p 4. order lpf 3 mhz lpf 3 mhz dem_out rssi standby logic vco xto 64 f cdem avcc rssi agnd dgnd mixvc c lnagnd lna_in data enable test mo d e lfgnd lfvcc xto lf dvcc lna data interface test br_0 br_1
4 4521c?rke?05/05 t5744 the xto is a one-pin oscillator that operates at the series resonance of the quartz crystal. according to figure 3-1 , the crystal should be connected to gnd via a capacitor cl. the value of that capacitor is recommended by the crystal supplier. the value of cl should be optimized for the individual board layout to achieve the exact value of f xto and hereby of f lo . when design- ing the system in terms of receiving bandwidth, the accuracy of the crystal and the xto must be considered. figure 3-1. pll peripherals the passive loop filter connected to pin lf is designed for a loop bandwidth of b loop = 100 khz. this value for b loop exhibits the best possible noise performance of the lo. figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth f lo is determined by the rf input frequency f rf and the if frequency f if using the following formula: f lo = f rf ? f if to determine f lo , the construction of the if filter must be considered at this point. the nominal if frequency is f if = 1 mhz. to achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency f xto . this means that there is a fixed relation between f if and f lo that depends on the logic level at pin mode. this is described by the following formulas: mode = 0 usa f if = f lo /314 mode = 1 europe f if = f lo /432.92 the relation is designed to achi eve the nominal if frequency of f if = 1 mhz for most applica- tions. for applications where f rf = 315 mhz, mode must be se t to '0'. in the case of f rf = 433.92 mhz, mode must be set to '1'. for other rf frequencies, f if is not equal to 1 mhz. f if is then dependent on the logical level at pin mode and on f rf . table 3-1 on page 5 summa- rizes the different conditions. the rf input either from an antenna or from a generator must be transformed to the rf input pin lna_in. the input impedance of that pin is provided in the electrical parameters. the para- sitic board inductances and capacitances also influence the input matching. the rf receiver t5744 exhibits its highest s ensitivity at the best signal-to-noise ratio in the lna. hence, noise matching is the best choice for designing the transformation network. dvcc xto lf lfvcc lfgnd v c c10 r1 c9 s l v s r1 = 820 ? c9 = 4.7 nf c10 = 1 nf
5 4521c?rke?05/05 t5744 a good practice when designing the network, is to start with power matching. from that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. if a saw is implemented into the input network a mirror frequency suppression of ? p ref = 40 db can be achieved. there are saws ava ilable that exhibit a notch at ? f = 2 mhz. these saws work best for an intermediate frequency of if = 1 mhz. the selectivity of the receiver is also improved by using a saw. in typical automotive applications, a saw is used. figure 3-2 shows a typical input matching network for f rf = 315 mhz and f rf = 433.92 mhz using a saw. figure 3-3 on page 6 illustrates the input matching to 50 ? without a saw. the input matching networks shown in figure 3-3 on page 6 are the reference networks for the parameters given in the electrical characteristics. figure 3-2. input matching network with saw filter table 3-1. calculation of lo and if frequency conditions local osci llator frequency intermediate frequency f rf = 315 mhz, mode = 0 f lo = 314 mhz f if = 1 mhz f rf = 433.92 mhz, mode = 1 f lo = 432.92 mhz f if = 1 mhz 300 mhz < f rf < 365 mhz, mode = 0 365 mhz < f rf < 450 mhz, mode = 1 f lo f rf 1 1 314 --------- - + ------------------- = f if f lo 314 --------- - = f lo f rf 1 1 432.92 ----------------- - + --------------------------- - = f if f lo 432.92 ----------------- - = in in_gnd out out_gnd case_gnd b3555 t5744 c3 22p l 25n c16 100p c17 8.2p l3 toko ll2012 f27nj 27n c2 8.2p l2 toko ll2012 f33nj 33n 1 2 3, 4 7, 8 5 6 8 9 rf in f rf = 433.92 mhz lnagnd lna_in in in_gnd out out_gnd case_gnd b3551 t5744 c3 47p l 25n c16 100p c17 22p l3 toko ll2012 f47nj 47n c2 10p l2 toko ll2012 f82nj 82n 1 2 3, 4 7, 8 5 6 8 9 f rf = 315 mhz lnagnd lna_in rf in
6 4521c?rke?05/05 t5744 figure 3-3. input matching network without saw filter please note that for all coupling conditions (see figure 3-2 on page 5 and figure 3-3 ), the bond wire inductivity of the lna ground is compensated. c3 forms a series resonance circuit together with the bond wire. l = 25 nh is a feed inductor to establish a dc path. its value is not critical but must be large enough not to detune the series resonance circuit. for cost reduction, this induc- tor can be easily printed on the pcb. this confi guration improves the sensitivity of the receiver by about 1 db to 2 db. 4. analog signal processing 4.1 if amplifier the signals coming from the rf front end are filtered by the fully integrated 4th-order if filter. the if center frequency is f if = 1 mhz for applications where f rf = 315 mhz or f rf = 433.92 mhz is used. for other rf input frequencies, refer to table 3-1 on page 5 to deter- mine the center frequency. the receiver t5744 employs an if bandwidth of b if = 600 khz and can be used together with the u2741b in ask mode. 4.2 rssi amplifier the subsequent rssi amplifier enhances the output signal of the if amplifier before it is fed into the demodulator. the dynamic range of this amplifier is drrssi = 60 db. if the rssi amplifier is operated within its linear range, the best s/n ratio is maintained. if the dynamic range is exceeded by the transmitter signal, the s/n ratio is defined by the ratio of the maximum rssi output voltage and the rssi output voltage due to a disturber. the dynamic range of the rssi amplifier is exceeded if the rf input signal is about 60 db higher compared to the rf input sig- nal at full sensitivity. 4.3 pin rssi the output voltage of the rssi amplifier (vrssi) is available at pin rssi. using the rssi output signal, the signal strength of different transmitte rs can be distinguished. the usable input power range p ref is ?100 dbm to ?55 dbm. since different rf input networks may exhibit slig htly different values for the lna gain, the sen- sitivity values given in the electrical characteri stics refer to a specific input matching. this matching is illustrated in figure 3-3 and exhibits the best possible sensitivity. t5744 c3 15p 25n 100p 3.3p toko ll2012 f22nj 22n 8 9 rf in f rf = 433.92 mhz lnagnd lna_in t5744 c3 33p 25n 100p 3.3p toko ll2012 f39nj 39n 8 9 f rf = 315 mhz lnagnd lna_in rf in
7 4521c?rke?05/05 t5744 figure 4-1. rssi characteristics 4.4 ask demodulator and data filter the signal coming from the rssi amplifier is conver ted into the raw data signal by the ask demodulator. an automatic threshold control circuit (atc) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. this circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. if the s/n ratio exceeds 10 db, the data signal can be detected properly. the output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. the data filter impro ves the s/n ratio as its passband can be adopted to the characteristics of the data signal. the data filter consists of a 1st-order highpass and a 1st-order lowpass filter. the highpass filter cut-off frequency is defined by an external capacitor connected to pin cdem. the cut-off frequency of the highpass filter is defined by the following formula: recommended values for cdem are given in the electrical characteristics. the cut-off frequency of the lowpass filter is defined by the selected baudrate range (br_range). br_range is defined by the pins br_0 and br_1. br_range must be set in accordance to the used baudrate. 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -130.0 -110.0 -90.0 -70.0 -50.0 -30.0 p ref (dbm) v rrsi (v) max. min. 25c 105c t amb = 40c table 4-1. definition of br_range by the pins br_0 and br_1 br_1 br_0 br_range 000 011 102 112 fcu_df 1 2 r 1 cdem ---------------------------------------------------- - =
8 4521c?rke?05/05 t5744 each br_range is defined by a minimum and a maximum edge-to-edge time (tee_sig). these limits are defined in the electrical characteristics. they should not be exceeded to maintain full sensitivity of the receiver. 4.5 receiving characteristics the rf receiver t5744 can be operated with and without a saw front-end filter. in a typical automotive application, a saw filter is used to achieve better selectivity. the selectivity with and without a saw front-end f ilter is illustrated in figure 4-1 on page 7 . note that the mirror fre- quency is reduced by 40 db. the plots are printe d relatively to the maxi mum sensitivity. if a saw filter is used, an insertion loss of about 4 db must be considered. when designing the system in te rms of receiving bandwidth, the lo deviation must be consid- ered as it also determines the if center frequen cy. the total lo deviation is calculated to be the sum of the deviation of the crystal and the xto deviation of the t5744. low-cost crystals are specified to be within 100 ppm. the xto devi ation of the t5744 is an additional deviation due to the xto circuit. this deviation is specified to be 30 ppm. if a crystal of 100 ppm is used, the total deviation is 130 ppm in that case. note that the receiving bandwidth and the if-filter band- width are equivalent. figure 4-2. receiving frequency response -100.0 -80.0 -60.0 -40.0 -20.0 0.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 df (mhz) dp (db) without saw with saw
9 4521c?rke?05/05 t5744 4.6 basic clock cycle of the digital circuitry the complete timing of the digital circuitry and the analog filtering is derived from one clock. according to figure 4-3 , this clock cycle tclk is derived from the crystal oscillator (xto) in com- bination with a divider. the division factor is controlled by the logical state at pin mode. according to chapter 'rf front end', t he frequency of the crystal oscillator (f xto ) is defined by the rf input signal (f rfin ) which also defines the operating frequency of the local oscillator (f lo ). figure 4-3. generation of the basic clock cycle pin mode can now be set in accordanc e with the desired clock cycle t clk . t clk controls the fol- lowing application-relevant parameters: timing of the analog and digital signal processing if filter center frequency (f if0 ) most applications are dominated by two transmission frequencies: f send = 315 mhz is mainly used in usa, f send = 433.92 mhz in europe. in order to ease the usage of all t clk -dependent parameters, the electrical characteristics display three conditions for each parameter. application usa (f xto = 4.90625 mhz, mode = l, t clk = 2.0383 s) application europe (f xto = 6.76438 mhz, mode = h, t clk = 2.0697 s) other applications (t clk is dependent on f xto and on the logical state of pin mode. the electrical characteristic is given as a function of t clk ). the clock cycle of some function blocks depends on the selected baud rate range (br_range) which is defined by the pins br_0 and br_1. this clock cycle t xclk is defined by the following formulas for further reference: br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk dvcc xto mode 16 15 14 t clk f xto xto divider :14/:10 l : usa(:10) h: europe(:14)
10 4521c?rke?05/05 t5744 5. pin enable via the pin enable the operating mode of the receiver can be selected (see figure 5-1 and fig- ure 5-2 ). if the pin enable is held to low, the receiver re mains in sleep mode. all circuits for signal pro- cessing are disabled and only the xto is running in that case. the current consumption is i s = i soff in that case. during the sleep mode the receiver is not sensitive to a transmitter signal. to activate the receiver, the pin enable must be held to high. during the start-up period, t startup , all signal processing circuits are enabled and settled. the duration of the start-up period depends on the selected baud-rate range (br_range). after the start-up period, all circuits are in a st able condition and the recei ver is in the receiving mode. in receiving mode, the internal data signal (dem_out) is switched to pin data. to avoid incor- rect timing at the begin of the data stream, the b egin is synchronized to a falling edge of the incoming data signal. the receiver stays in the receiving mode until it is switched back to sleep mode via pin enable. during start-up and receiving mode, the current consumption is i s = i son . figure 5-1. enable timing (1) figure 5-2. enable timing (2) dem_out enable data sleep mode start-up mode receiving mode i s = i soff i s = i son i s = i son t start-up t ee_sig dem_out enable data sleep mode start-up mode receiving mode i s = i soff i s = i son i s = i son t start-up t ee_sig
11 4521c?rke?05/05 t5744 6. digital signal processing the data from the ask demodulator (dem_out) is digitally processe d in different ways and as a result converted into the output signal data. th is processing depends on the selected baudrate range (br_range). figure 6-1 on page 11 illustrates how dem_out is synchronized by the extended basic clock cycle t xclk . data can change its state only after t xclk has elapsed. the edge-to-edge time period tee_sig of the data signal as a result is always an integral multiple of t xclk . the minimum time period between two edges of the data signal is limited to tee_sig t data_min . this implies an efficient suppression of spikes at the data output. at the same time it limits the maximum frequency of edges at data. this eases the interrupt handling of a connected microcontroller. figure 6-1. synchronization of the demodulator output figure 6-2. debouncing of the demodulator output data_out (data) t xclk dem_out t ee_sig data dem_out t ee t ee t data_min t ee t data_min t data_min
12 4521c?rke?05/05 t5744 7. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit supply voltage v s 6v power dissipation p tot 450 mw junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c maximum input level, input matched to 50 ? p in_max 10 dbm 8. thermal resistance parameters symbol value unit junction ambient so20 package r thja 100 k/w junction ambient sso20 package r thja 100 k/w
13 4521c?rke?05/05 t5744 9. electrical characteristics all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (v s = 5v, t amb = 25c) parameters test conditions symbol 6.76438 mhz osc. (mode:1) 4.90625 mhz osc. (mode:0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. basic clock cycle of the digital circuitry basic clock cycle mode = 0 (usa) mode = 1 (europe) t clk 2.0697 2.0697 2.0383 2.0383 1/(f xto /10) 1/(f xto /14) 1/(f xto /10) 1/(f xto /14) s s extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s start-up time (see figure 5-1 and figure 5-2 on page 10 ) br_range0 br_range1 br_range2 br_range3 t startup 1855 1061 1061 663 1855 1061 1061 663 1827 1045 1045 653 1827 1045 1045 653 896.5 512.5 512.5 320.5 t clk 896.5 512.5 512.5 320.5 t clk s s s s s receiving mode intermediate frequency mode=0 (usa) mode=1 (europe) f if 1.0 1.0 f xto 64/314 f xto 64/432.92 mhz mhz minimum time period between edges at pin data br_range0 br_range1 br_range2 br_range3 ( figure 6-2 on page 11 ) t data_min 165 83 41.4 20.7 165 83 41.4 20.7 163 81 40.7 20.4 163 81 40.7 20.4 10 t xclk 10 t xcl 10 t xclk 10 t xclk 10 t xclk 10 t xcl 10 t xclk 10 t xclk s s s s edge to edge time period of the data signal for full sensitivity br_range0 br_range1 br_range2 br_range3 ( figure 5-1 on page 10 ) t ee_sig 400 200 100 50 8479 8479 8479 8479 400 200 100 50 8350 8350 8350 8350 br_range 2 s/t clk 4097 t clk s s s s 10. electrical characteristics (continued) parameters test conditions symbol min. typ. max. unit current consumption sleep mode (xto active) is off 190 276 a ic active (startup-, receiving mode) pin data = h is on 7.1 8.7 ma lna mixer third-order intercept point lna/ mixer/ if amplifier input matched according to figure 3-3 on page 6 iip3 ?28 dbm lo spurious emission at rf in input matched according to figure 3-3 on page 6 , required according to i-ets 300220 is lorf ?73 ?57 dbm noise figure lna and mixer (dsb) input matching according to figure 3-3 on page 6 nf 7 db lna_in input impedance at 433.92 mhz at 315 mhz zi lna_in 1.0 || 1.56 1.3 || 1.0 k ? || pf k ? || pf
14 4521c?rke?05/05 t5744 1 db compression point (lna, mixer, if amplifier) input matched according to figure 3-3 on page 6 , referred to rf in ip 1db ?40 dbm maximum input level input matched according to figure 3-3 on page 6 , ber 10 -3 p in_max ?20 dbm local oscillator operating frequency range vco f vco 299 449 mhz phase noise vco/lo f osc = 432.92 mhz at 1 mhz at 10 mhz l (fm) ?93 ?113 ?90 ?110 dbc/hz dbc/hz spurious of the vco at f xto ?55 ?47 dbc vco gain k vco 190 mhz/v loop bandwidth of the pll for best lo noise (design parameter) r1 = 820 ? c9 = 4.7 nf c10 = 1 nf b loop 100 khz capacitive load at pin lf c lf_tot 10 nf xto operating frequency xto crystal frequency, appropriate load capacitance must be connected to xtal f xtal = 6.764375 mhz (eu) f xtal = 4.90625 mhz (us) f xto 6.764375 ?30 ppm 4.90625 ?30 ppm 6.764375 4.90625 6.764375 +30 ppm 4.90625 +30 ppm mhz mhz series resonance resistor of the crystal f xto = 6.764 mhz 4.906 mhz r s 150 220 ? ? static capacitance of the crystal c o 6.5 pf analog signal processing input sensitivity input matched according to figure 3-3 ask (level of carrier) ber 10 -3 (manchester), f in = 433.92 mhz/ 315 mhz t = 25c, v s = 5v, f if = 1 mhz p ref_ask br_range0 (1 kbd) ?107 ?110 ?112 dbm br_range1 (2 kbd) ?105 ?108 ?110 dbm br_range2 (4kbd) ?103 ?106 ?108 dbm br_range3 (8 kbd) ?101 ?104 ?106 dbm sensitivity variation for the full operating range compared to t amb = 25 c, v s = 5v f in = 433.92 mhz/315 mhz f if = 1 mhz p ask = p ref_ask + ? p ref ? p ref +2.5 ?1.5 db 10. electrical characteristics (continued) parameters test conditions symbol min. typ. max. unit
15 4521c?rke?05/05 t5744 sensitivity variation for full operating range including if filter compared to t amb = 25c, v s = 5v f in = 433.92 mhz/ 315 mhz f if = 0.79 mhz to 1.21 mhz f if = 0.73 mhz to 1.27 mhz p ask = p ref_ask + ? p ref ? p ref +5.5 +7.5 ?1.5 ?1.5 db db s/n ratio to suppress inband noise signals snr 10 12 db dynamic range rssi amplifier ? r rssi 60 db rssi output voltage range v rssi 1.0 3.0 v rssi gain g rssi 20 mv/db ri of pin cdem for cut-off frequency calculation r i 28 40 55 k ? recommended cdem for best performance br_range0 br_range1 br_range2 br_range3 cdem 33 18 10 6.8 nf nf nf nf upper cut-off frequency data filter upper cut-off frequency br_range0 br_range1 br_range2 br_range3 f u 1.75 3.5 7.0 14.0 2.2 4.4 8.8 17.6 2.65 5.3 10.6 21.2 khz khz khz khz digital ports data output - saturation voltage low - internal pull-up resistor i ol = 1 ma v oi r pup 39 0.08 50 0.3 65 v k ? enable input - low-level input voltage - high-level input voltage sleep mode receiving mode v il v ih 0.8 v s 0.2 v s v v mode input - low-level input voltage - high-level input voltage division factor = 10 division factor = 14 v il v ih 0.8 v s 0.2 v s v v br_0 input - low-level input voltage - high-level input voltage v il v ih 0.8 v s 0.2 v s v v br_1 input - low-level input voltage - high-level input voltage v il v ih 0.8 v s 0.2 v s v v test input - low-level input voltage test input must always be set to low v il 0.2 v s v 10. electrical characteristics (continued) parameters test conditions symbol min. typ. max. unit fcu_df 1 2 r 1 cdem ----------------------------------------------------- =
16 4521c?rke?05/05 t5744 figure 10-1. application circuit: f rf = 433.92 mhz, without saw filter figure 10-2. application circuit: f rf = 315 mhz, without saw filter 8 10 9 7 20 5 6 4 2 3 1 19 18 17 16 15 14 13 12 11 c6 10 nf 10% c13 c14 10 nf 10% 10% c8 150 pf np0 5% 1 nf 5% 5% c9 c10 4.7 nf 10% br_1 br_0 cdem data enable test rssi mode avcc agnd mixvcc xto dgnd lfgnd lfvcc lf lnagnd nc lna_in dvcc c15 150 pf np0 c11 t5744 12 pf np0 c3 5% 22 nh q1 6.7643 mhz 15 pf 39 nf 5% c12 10 nf 10% enable rssi data c7 2.2 f 10% coax gnd v s c16 c17 5% 100 pf np0 5% 3.3 pf np0 l2 + r1 820 ? 5% np0 2% 8 10 9 7 20 5 6 4 2 3 1 19 18 17 16 15 14 13 12 11 c6 10 nf 10% c13 c14 10 nf 10% 10% c8 150 pf np0 5% 1 nf 5% 5% c9 c10 4.7 nf 10% br_1 br_0 cdem data enable test rssi mode avcc agnd mixvcc xto dgnd lfgnd lfvcc lf lnagnd nc lna_in dvcc c15 150 pf np0 c11 t5744 15 pf np0 c3 5% 39 nh q1 4.90625 mhz 33 pf 39 nf 5% c12 10 nf 10% enable rssi data c7 2.2 f 10% coax gnd v s c16 c17 5% 100 pf np0 5% 3.3 pf np0 l2 + r1 820 ? 5% np0 2%
17 4521c?rke?05/05 t5744 figure 10-3. application circuit: f rf = 433.92 mhz, with saw filter figure 10-4. application circuit: f rf = 315 mhz, with saw filter 8 10 9 7 20 5 6 4 2 3 1 19 18 17 16 15 14 13 12 11 c6 10 nf 10% c13 c14 10 nf 10% 10% c8 150 pf np0 5% 1 nf 5% 5% c9 c10 4.7 nf 10% br_1 br_0 cdem data enable test rssi mode avcc agnd mixvcc xto dgnd lfgnd lfvcc lf lnagnd nc lna_in dvcc c15 150 pf np0 c11 t5744 12 pf np0 c3 q1 6.76438 mhz 22 pf 39 nf 5% c12 10 nf 10% enable rssi data c7 2.2 f 10% gnd v s + r1 820 ? 5% np0 2% 5% 27 nh coax 5% 100 pf np0 5% c2 8.2 pf 5% 33 nh l2 l3 in_gnd case_gnd case_gnd in out out_gnd 15 26 5% 8.2 pf np0 48 37 b3555 c16 c17 8 10 9 7 20 5 6 4 2 3 1 19 18 17 16 15 14 13 12 11 c6 10 nf 10% c13 c14 10 nf 10% 10% c8 150 pf np0 5% 1 nf 5% 5% c9 c10 4.7 nf 10% br_1 br_0 cdem data enable test rssi mode avcc agnd mixvcc xto dgnd lfgnd lfvcc lf lnagnd nc lna_in dvcc c15 150 pf np0 c11 t5744 15 pf np0 c3 q1 4.90625 mhz 47 pf 39 nf 5% c12 10 nf 10% enable rssi data c7 2.2 f 10% gnd v s + r1 820 ? 5% np0 2% 5% 47 nh coax 5% 100 pf np0 5% c2 10 pf 5% 82 nh l2 l3 in_gnd case_gnd case_gnd in out out_gnd 15 26 5% 22 pf np0 48 37 b3551 c16 c17
18 4521c?rke?05/05 t5744 12. package information 11. ordering information extended type number package remarks t5744n-tks sso20 tube t5744n-tkq sso20 taped and reeled t5744n-tgs so20 tube t5744n-tgq so20 taped and reeled technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110
19 4521c?rke?05/05 t5744 13. revision history technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 110 please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4521c-rke-05/05 ? put datasheet in a new template ? figure 1-1 ?system block diagram? on page 1 changed ? new heading rows at table ?absolute maximum ratings? on page 12 added ? table ?electrical characteristics? on page 13 changed ? table ?ordering information? on page 18 changed
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